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Figure 6.1: Inverted pendulum.

mem-pendulum

Figure 6.3: High level view of a 128-bit 16 x 8 DRAM chip.

mem-dramarray

Figure 6.4: Reading the contents of a DRAM supercell.

mem-dramras

Figure 6.4: Reading the contents of a DRAM supercell.

mem-dramcas

Figure 6.5: Reading the contents of a memory module.

mem-drammodule

Figure 6.6: Typical bus structure that connects the CPU and main memory.

mem-membus

Figure 6.7: Memory read transaction for a load operation: movl A,%eax.

mem-memread1

Figure 6.7: Memory read transaction for a load operation: movl A,%eax.

mem-memread2

Figure 6.7: Memory read transaction for a load operation: movl A,%eax.

mem-memread3

Figure 6.8: Memory write transaction for a store operation: movl %eax,A.

mem-memwrite1

Figure 6.8: Memory write transaction for a store operation: movl %eax,A.

mem-memwrite2

Figure 6.8: Memory write transaction for a store operation: movl %eax,A.

mem-memwrite3

Figure 6.9: Disk geometry.

mem-surface

Figure 6.9: Disk geometry.

mem-cylinder

Figure 6.10: Disk dynamics.

mem-arm

Figure 6.10: Disk dynamics.

mem-cylinderarms

Figure 6.11: Typical bus structure that connects the CPU, main memory, and I/O devices.

mem-iobus

Figure 6.12: Reading a disk sector.

mem-diskread1

Figure 6.12: Reading a disk sector.

mem-diskread2

Figure 6.12: Reading a disk sector.

mem-diskread3

Figure 6.16: The increasing gap between DRAM, disk, and CPU speeds.

mem-cpumemgap

Figure 6.21: The memory hierarchy.

mem-memhier

Figure 6.22: The basic principle of caching in a memory hierarchy.

mem-cacheconcept

Figure 6.24: Typical bus structure for L1 and L2 caches.

mem-cachebus

Figure 6.25: General organization of cache (S, E, B, m).

mem-cacheorg

Figure 6.25: General organization of cache (S, E, B, m).

mem-physaddr

Figure 6.27: Direct-mapped cache (E = 1).

mem-dmcacheorg

Figure 6.28: Set selection in a direct-mapped cache.

mem-dmcacheindex

Figure 6.29: Line matching and word selection in a direct-mapped cache.

mem-dmcachematch

Figure 6.31: Why caches index with the middle bits.

mem-middlebits

Figure 6.32: Set associative cache (1 < E < C/B).

mem-sacacheorg

Figure 6.33: Set selection in a set associative cache.

mem-sacacheindex

Figure 6.34: Line matching and word selection in a set associative cache.

mem-sacachematch

Figure 6.35: Fully set associative cache (E = C/B).

mem-facacheorg

Figure 6.36: Set selection in a fully associative cache.

mem-facacheindex

Figure 6.37: Line matching and word selection in a fully associative cache.

mem-facachematch

Figure 6.38: A typical multi-level cache organization.

mem-multilevel

Figure 6.42: The memory mountain.

mem-xeonmountain

Figure 6.43: Ridges of temporal locality in the memory mountain.

mem-xeoncaches

Figure 6.44: A slope of spatial locality.

mem-xeonlines

Figure 6.47: Pentium III Xeon matrix multiply performance.

mem-xeonmm

Figure 6.49: Graphical interpretation of blocked matrix multiply

mem-bmmidea

Figure 6.50: Pentium III Xeon blocked matrix multiply performance.

mem-xeonbmm

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